Torii Naoya（Professor）

TORII NAOYA

Specialized field Information security, High speed implementation of encryption algorithms, Cryptographic module, Side channel attack countermeasures, Countermeasures against cyber-attacks, Digital Content Protection
Classes Project Studies A
Project Studies B
Introduction of Information Systems
Case Study 1
Case Study 2
Computer Network Laboratory
Computer Networks 1
Information security
Research theme Cyber-Physical System Security

Application for coverage

Information Systems Science of Graduate school of engineering

  • Major fields Information security, High speed implementation of encryption algorithms, Cryptographic module, Side channel attack countermeasures, Countermeasures against cyber-attacks, Digital Content Protection
    Research Theme Cyber-Physical System Security
    Disciplinary Educational background and Doctorate
    1981 B.S. (in engineering), Osaka University
    1983 M.S. (in engineering), Osaka University
    2017 Ph.D (in engineering), Yokohama National University

    R&D Career History
    April 2018: Professor, Faculty of Science & Engineering, Soka University
    July 2014 – March 2018: Fujitsu Laboratories Ltd.
    • Knowledge Information Processing Laboratory and Security Research Laboratory
    •Responsible for R&D and commercialization strategy on information security
    April 2004 - June 2014: Fujitsu Laboratories Ltd.
    • Secure Computing Laboratory
    •Responsible for R&D of information security including security evaluation of cryptography, tamper resistance, Cloud security, Countermeasures against cyber attacks, privacy protection, and biometric authentication system
    April 2000 - March 2004: Fujitsu Laboratories Ltd.
    •Computer system laboratories.
    •Responsible for R&D of development of symmetric key encryption algorithm (SC2000)
    April 1996 – March 2000: Fujitsu Laboratories Ltd.
    •S project
    •Engaged in R&D on high-speed implementation of encryption algorithms
    September 1990 – March 1996: Fujitsu Laboratories Ltd.
    •Distribution system laboratory
    •Engaged in R&D on systems applying encryption technology, such as ID-based key management system and Super-distribution system for contents protection.
    July 1989 – August 1990: Visiting scholar at the George Washington University in Washington DC (U.S.A)
    July 1987 – June 1989: Fujitsu Laboratories Ltd.
    •Information communication laboratory
    •Engaged in R&D on high-speed hardware implementation of public key cryptography.
    April 1983 – June 1987: Fujitsu Laboratories Ltd.
    •Digital network laboratory
    •Engaged in R&D on analog scrambler for cordless telephones

     
    Publications Naoya Torii, Hirotaka Kokubo, Dai Yamamoto, Kouichi Itoh, Masahiko Takenaka, and Tsutomou Matsumoto, “ASIC implementation of random number generators using SR latches and its evaluation,” EURASIP Journal on Information Security 2016 2016:10
    Naoya Torii, Dai Yamamoto, Masahiko Takenaka, and Tsutomu Matsumoto, “Experimental Evaluation on the Resistance of Latch PUFs Implemented on ASIC against FIB-Based Invasive Attacks,” IEICE Trans. Fundamentals, Vol. E99-A, No.1, pp.118-129, Jan. 2016.
    Kouichi Itoh, Takao Ochiai, and Naoya Torii.Power Attack Using Chosen Message against Diffie-Hellman Scheme. IEICE transactions on fundamentals of electronics, communications and computer sciences (Japanese edition), vol. J95-A, No.5, pp436-445, 2012.
    Kouichi Itoh, Dai Yamamoto, Kazuyoshi Furukawa, Tetsuya Izu, Masahiko Takenaka, and Naoya Torii.Power Attack Using Chosen Message against Elliptic Scalar Multiplication. IEICE transactions on fundamentals of electronics, communications and computer sciences (Japanese edition), vol. J95-A, No.5, pp446{455, 2012.
    Dai Yamamoto, Kazuo Sakiyama, Mitsugu Iwamoto, Kazuo Ohta, Masahiko Takenaka, Kouichi Itoh, and Naoya Torii, “A new method for enhancing variety and maintaining reliability of PUF responses and its evaluation on ASICs,” J. Cryptographic Engineering, Vol.5(3), pp.187-199, 2015.
    Shoichi MASUI, Kenji MUKAIDA, Masahiko TAKENAKA, and Naoya Torii, “Design Optimization of a High-Speed, Area-Efficient and Low-Power Montgomery Modular Multiplier for RSA Algorithm,” IEICE Trans. Electron., Vol.E88-C, No4. pp576-58, 2005.
    International Conferences Naoya. Torii, Dai. Yamamaoto, Tsutomu. Matsumoto, “Evaluation of Latch-based PUFs Implemented on 40nm ASICs,” 2016 Fourth International Symposium on Computing and Networking (CANDAR), pp. 642-648, 2016.
    Naoya. Torii, Dai. Yamamaoto, Tsutomu. Matsumoto, “Evaluation of Latch-based Physical Random Number Generator Implementation on 40nm ASICs,” In Proc. of the 6th International Workshop on Trustworthy Embedded Devices (TrustED '16), ACM, pp. 23-30, 2016.
    Dai Yamamoto, Masahiko Takenaka, Kazuo Sakiyama, and Naoya Torii, “A Technique using PUFs for Protecting Circuit Layout Designs against Reverse Engineering,” In Proc. International Workshop on Security 2014 (IWSEC’ 14), Lecture Notes in Computer Science 8639, Springer-Verlag, pp.158-253, 2014.
    Dai Yamamoto, Masahiko Takenaka, Kazuo Sakiyama, and Naoya Torii, “Security Evaluation of Bistable Ring PUFs on FPGAs using Differential and Linear Analysis,” In Proc. The Federated Conference on Computer Science and Information Systems (FedCSIS), 1st Workshop on Emerging Aspects in Information Security (EAIS '14), IEEE, pp.911-918,2014.
    Tetsuya Izu, Yumi Sakemi, Masahiko Takenaka, and Naoya Torii, “A Spoofing Attack against a Cancelable Biometric Authentication Scheme,” AINA2014, pp.234-239, IEEE, 2014.
    Hirotaka Kokubo, Dai Yamamoto, Masahiko Takenaka, Kouichi Itoh and Naoya Torii, “Evaluation of ASIC Implementation of Physical Random Number Generators using RS Latches,” 12th Smart Card Research and Advanced Application Conference 2013.
    Kenji MUKAIDA, Shoichi MASUI, Masahiko TAKENAKA, and Naoya Torii, “Design of high-speed and area-efficient Montgomery modular multiplier for RSA algorithm,” IEEE VLSI Circuits 2004, pp. 320 - 323, 2004 Date 17-19 June 2004.
    Kouichi Itoh, Jun Yajima, Masahiko Takenaka, and Naoya Torii, “DPA Countermeasures by Improving the Window Method Cryptographic Hardware and Embedded Systems,” CHES 2002, Lecture Notes in Computer Science Volume 2523, pp 303-317, 2003
    Kouichi Itoh, Masahiko Takenaka, and Naoya Torii, “DPA Countermeasure Based on the “Masking Method,” Information Security and Cryptology,” ICISC 2001, Lecture Notes in Computer Science 2288, pp 440-456, 2002.
    Takeshi Shimoyama, Hitoshi Yanami, Kazuhiro Yokoyama, Masahiko Takenaka, Kouichi Itoh, Jun Yajima, and Naoya Torii, Hidema Tanaka, “The Block Cipher SC2000,” Fast Software Encryption 2001, Lecture Notes in Computer Science Volume 2355, pp 312-327, 2002
    Souichi Okada, Naoya Torii, Kouichi Itoh, and Masahiko Takenaka, “Implementation of Elliptic Curve Cryptographic Coprocessor over GF(2＾m) on an FPGA Cryptographic Hardware and Embedded Systems,” CHES 2000, Lecture Notes in Computer Science Volume 1965, pp 25-40, 2000.
    Membership of Academic Societies 1981-present: Member of IEICE (The Institute of Electronics, Information and Communication Engineers)
    •1980-present: Member of IEEE (The Institute of Electrical and Electronics Engineers).
    •2011-present: Member of IPSJ (Information Processing Society of Japan)

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